This invention relates to clock driver integrated circuits (IC""s), and more particularly to reducing skew between output drivers.
Many complex computer, network, or other electronic systems sequence through a series of states during operation. These states are often defined on a fundamental level by binary states of flip-flops or registers that store inputs when a clock input rises or falls. Design of such systems is facilitated by using clock signals that are synchronized to one another, so that many or all of the flip-flops are clocked at the same time. Such systems are known as synchronous circuits.
Some systems can have thousands of flip-flops that have clock inputs derived from a single clock source or reference. Although different flip-flops may receive local clock signals that are buffered or even gated by other logic signals, these local clock signals can be traced upstream to a common clock source.
FIG. 1 shows a clock tree. Master clock source 10 generates a master or reference clock, perhaps from a clock input to a chip, or from a pair of inputs connected to an external crystal or oscillator, or even internally from a ring oscillator. First-level buffer 14 buffers the reference clock, ensuring that downstream loading or coupling does not effect master clock source 10. Second-level buffers 16 fan out the buffered reference clock to produce several secondary clocks. These secondary clocks drive the many inputs to clock buffers 12, each of which drives a clock line Y1, Y2, . . . Y(N). These clock lines can be routed internally to registers, state machines, and flip-flops, or can be external buffers that drive off-chip clocks to other chips in the system. Having many clock output lines allows line loading to be more evenly distributed. When loads are evenly distributed, clock skews can be minimized.
FIG. 2 is a waveform highlighting clock skew between clock lines. Clock signals can be measured at the point in time when their voltages cross over a threshold voltage Vth. Clock signal Y(J) for the Jth clock line is somewhat faster than clock signal Y(K) for the Kth clock line. The difference in time that the two clock signals cross the threshold is known as the clock skew. Clock skews for rising and falling edges usually differ slightly.
The maximum clock skew occurs when output Y(J) is the fastest of all N clock lines, and output Y(K) is the slowest of all clock lines. This maximum clock skew limits the maximum frequency that the reference clock can operate at. For example, if the clock skew were as large as the clock period, one flip-flop driven by a fast clock line could be clocked twice before a flip-flop driven by a slow clock line is clocked once. Data could be fed through faster-clocked flip-flops and get ahead of data in slower-clock flip-flops.
Even when clock loads are distributed evenly among the clock lines, some clock skew still occurs due to parasitic resistances within a clock driver chip. FIG. 3 highlights clock skews caused by physical layouts of clock drivers along power and ground busses in a clock driver chip. Second-level buffer 16 drives a group of pre-drivers 20, 21, 22, . . . 28. Each pre-driver 20-28 drives a pre-drive line P1, P2, P3 . . . PN, which is an input to output buffers 30, 31, 32, . . . 38. Output buffers 30-38 drive clock output lines Y1, Y2, Y3, . . . YN.
In an actual integrated circuit chip, outputs Y1, Y2, Y3 . . . YN are spread around the perimeter of the chip, driving large output bonding pads that have metal wires bonded to them. Other pads are bonded to power-supply and ground wires. The distance from the power pad to each pre-driver varies with the location of the output pad. Likewise, the distance from the ground pad to each pre-driver also varies.
Outputs that are farther away from the ground or power pad have a larger parasitic resistance in the power or ground connection. For example, pre-driver 22 has three resistors 18 between its power input V3 and the power pad, while pre-driver 20 has only one resistor 18 in its s power input V1 power path. Last pre-driver 28 has N resistors 18 in its power input VN.
The ground pad is often located away from the power pad. In this example, the ground pad is located at the opposite side of the N outputs from the power pad. Thus second pre-driver 21 has two resistors 18 from its power input V2 to the power pad, but N-1 resistors 19 from its ground input G2 to the ground pad.
Although power and ground bus topology differs for different chip designs, these distributed resistances and capacitances always cause skew. For example, first pre-driver 20 has a short connection to power, but a long connection to ground. Pre-drive line P1 may have a faster rise time that other pre-drivers, due to the short path to power, but a longer fall time, due to the long path to ground.
Although the parasitic resistors 18, 19 are small, large currents can pass through, especially for clock driver chips where all outputs change simultaneously. These large simultaneous currents can cause a significant I*R voltage shift in the power and ground busses.
FIG. 4 is a waveform showing clock skew due to power and ground bus resistances. The reference clock changes, causing pre-driver lines P1, P2, PN to rise. This pulls current from the power bus, through parasitic resistors 18 of FIG. 3. Since only 1 resistor 18 is in the path to power input V1 of first pre-driver 20, V1 drops only slightly. However, V2 drops almost twice as much, since 2 resistors are in the path to V2. Power input VN to the last pre-driver experiences a large drop due to the N resistors 18 in its power path.
The reduced power input voltages V2, VN slow the rise time of pre-driver lines P2, PN, with the slowdown of PN especially pronounced. Since the pre-drivers contain at least 2 inverting stages, some current is also sunk to ground, causing ground bounce on G1, G2, GN. This also slows the propagation to pre-driver lines P1, P2, PN.
The added delay for the rise of PN causes a skew between P1 and PN. This clock skew is caused by different lengths and resistances of internal paths to power and ground. While these resistances can be reduced by using wider internal power and ground busses, they are a cause of clock skew.
What is desired is clock driver chip with reduced clock skew. It is desired to reduce skew between clock outputs.
A parallel clock driver has a reference clock and a plurality of pre-driver circuits that are responsive to the reference clock. Each pre-driver circuit outputs a pull-up pre-driver line and a pull-down pre-driver line and receives an enable signal having an enabling state that enables the pre-driver circuit to drive high and low the pull-up and pull-down pre-driver lines in response to the reference clock. A plurality of output buffers each have a pull-up transistor with a gate driven by the corresponding pull-up pre-driver line, and a pull-down transistor with a gate driven by the corresponding pull-down pre-driver line. Each drives a clock output with the pull-up transistor and the pull-down transistor. A plurality of shorting switches each receives a pair of the enable signals for a pair of the pre-driver circuits. The shorting switch connects together the pull-up pre-driver lines generated by the pair of pre-driver circuits when the pair of enable signals is both in the enabling state. Thus the pull-up pre-driver lines are connected together by the shorting switch when the pair of the pre-driver circuits are both enabled.